ESP32-P4-WIFI6 7 Zoll Touch Display Entwicklungsboard, Basierend auf ESP32-P4 und ESP32-C6, 7" IPS Bildschirm 1024x600, mit RS485/CAN/I2C/UART Headern, Unterstützt AI Sprachinteraktion
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Beschreibung
Amazon
ESP32-P4-WIFI6 7inch Touch Display Development Board, adopts ESP32-P4-Core module, onboard ESP32-C6-MINI module extends 2.4GHz Wi-Fi 6 and Bluetooth 5 (LE), high-performance MCU with RISC-V 32-bit dual-core and single-core processors Equipped with 7inch IPS touch screen, 1024 × 600 resolution, capacitive 5-point touch, 160° wide viewing angle, 16.7M color, 350cd/m² brightness 128 KB HP ROM, 16 KB LP ROM, 768 KB HP L2MEM, 32 KB LP S-R-A-M, 8 KB TCM. 32MB PSRAM in the chip's package, with onboard 32MB Nor Flash Provides image and voice processing interfaces, powerful image and voice processing capability. Rich human-machine Interfaces such as MIPI-CSI, MIPI-DSI, USB 2.0 OTG HS, SDIO 3.0 TF card slot, dual microphones (supports echo cancellation), speaker header and RTC battery holder, etc. Onboard RS485, CAN, I2C, and UART headers for easy communication with industrial equipments. Adapting 2*12 GPIO header with 17 x remaining programmable GPIOs
ESP32-P4-WIFI6 7inch Touch Display Development Board, adopts ESP32-P4-Core module, onboard ESP32-C6-MINI module extends 2.4GHz Wi-Fi 6 and Bluetooth 5 (LE), high-performance MCU with RISC-V 32-bit dual-core and single-core processors Equipped with 7inch IPS touch screen, 1024 × 600 resolution, capacitive 5-point touch, 160° wide viewing angle, 16.7M color, 350cd/m² brightness 128 KB HP ROM, 16 KB LP ROM, 768 KB HP L2MEM, 32 KB LP S-R-A-M, 8 KB TCM. 32MB PSRAM in the chip's package, with onboard 32MB Nor Flash Provides image and voice processing interfaces, powerful image and voice processing capability. Rich human-machine Interfaces such as MIPI-CSI, MIPI-DSI, USB 2.0 OTG HS, SDIO 3.0 TF card slot, dual microphones (supports echo cancellation), speaker header and RTC battery holder, etc. Onboard RS485, CAN, I2C, and UART headers for easy communication with industrial equipments. Adapting 2*12 GPIO header with 17 x remaining programmable GPIOs